A 12b 400MS/s 4-Time Interleaved Pipelined-SAR ADC with Fully Differential Bias-enhanced Ring Amplifier

A 12-bit 400MS/s 4-channel time-interleaved pipelined-SAR ADC with a fully differential bias-enhanced ring amplifier for low-power and high-speed application is presented. The sub-ADC adopts a two-stage pipeline quantization scheme with a 6-bit SAR ADC in the first stage and a 7-bit SAR ADC in the second stage with 1-hit overlapping. To further optimize the speed of the sub-ADCs, a bias-enhanced ring amplifier is proposed. A prototype ADC is designed and simulated in 65nm CMOS technology with a standard 1.2 V supply voltage. With the least-mean-square algorithm calibration, this ADC achieves SNDR of 64.5 dB and SFDR of 86.6 dB. The whole ADC consumes 10.3mW, achieving a FoM of 19.9 fJ/conv-step.