A “Kuznyechik” Block Cipher Accelerator for RISC-V System-on-Chip

Kuznyechik is the Russian symmetric block cipher algorithm that has been introduced in the National Standard of the Russian Federation GOST R 34.12-2015. It provides higher security against mathematical cryptanalysis at the cost of higher computing complexity. In this study, a Kuznyechik accelerator for RISC-V System-on-Chip is proposed to significantly improve the encryption/decryption times of the Russian symmetric block cipher algorithm. Compared to the execution time of an open-source Kuznyechik software implementation, that of the proposed accelerator is reduced by 1597.8 fold. The proposed accelerator has a maximum operating frequency of 124.01 MHz, with a maximum encryption/decryption throughput of 283.45 Mbps. When being deployed on a Xilinx Kintex-7 FPGA device, the proposed Kuznyechik accelerator utilizes a relatively small amount of hardware resources, including 6175 Slice Look-up-Tables (LUTs), 2725 Slice Registers and 4 Block RAM (BRAM), which is 9.74%, 2.15% and 2.96% of available Slice LUTs, Slice Registers and Block RAM, respectively.