Design of the Self-Biased PLL Based Low-Power Low-Jitter Multi-Phase Clock Generator: An Overview (Invited Paper)

Multiphase clock generator (MPCG) is an essential building block in high-speed wireless or wireline communication circuits. Compared with other widely used MPCGs, including divider, delay-locked loop and injection-locked oscillators, the self-biased phased-locked loop based MPCG (SBPLL-MPCG) is more attractive to generate a low-jitter clock with lower power. This paper presents an overview of the SBPLL-MCG, including the operation principles, advantages, and two design examples of the MPCG used in a 32-Gb/s PAM4 clock-and-data recovery (CDR) and a 64-Gb/s reference-less PAM4 CDR, respectively.