The Design and Analysis for Improving the Power-Efficiency of Ring-VCO Based PLL (Invited Paper)

The ring-VCO-based clock generator has gained much interest due to its compact area but suffers from poor performance. To enhance power efficiency while maintaining performance, this paper presents several promising techniques and provides a detailed analysis, including a discussion of the jitter impact on analog-to-digital converters (ADCs). This examination aims to facilitate a more comprehensive evaluation of phase locked loops (PLLs) performance straightforwardly and accurately.