Design and Automation Methodology of a Wideband, High-PSRR LDO Using Device Look-up Tables

This work presents a Look-up Table (LuT)-based methodology for designing wideband, high Power Supply Re-jection Ratio (PSRR) Low Dropout Regulators (LDOs). The proposed design methodology has been automated using a Python script to produce optimal sizes for all LDO transistors. A high-PSRR LDO has been designed in 180-nm CMOS technology, utilizing this methodology and its automation script. The LDO achieves a DC-PSRR of -60 dB, with peak PSRR of -36 dB across frequencies and load currents. Across the stability performance metrics, an error percentage of less than 2.5% is achieved between calculated and simulated values. The presented design approach addresses the limitations of traditional MOSFET square-law model in advanced CMOS technology nodes while retaining the analytical insights and design intuition, and therefore, reduces design iterations and the overall design cycle.