Look-Up Table-Based Digital Calibration for the Correction of Pipeline Analog-to-Digital Converter Non-Idealities

This paper presents an agile digital calibration technique for fast error correction in inter-stage residue amplifiers used in pipelined analog-to-digital converters (ADCs). Four equally spaced DC test inputs on a segment of the ADC transfer curve are required to determine the non-ideal characteristics of the transfer curve. The data collected during characterization is used to measure and correct the amplifier’s non-linearity limitations as well as gain errors. A major advantage of the proposed calibration approach is that it avoids the need for complex on-chip computations for error correction. Instead, a look-up table stores the error codes associated with the amplifier’s non-idealities. During regular operation, the digital controller fetches the corrective error data to complete the ADC linearization procedure, eliminating the need for additional circuitry or complex on-chip computations. The proposed calibration technique is highly agile and minimizes ADC operation interruptions for re-calibration, requiring only 50 clock cycles if measurement redundancy is included. Simulation results for a 13-bit pipeline ADC designed in the 40-nm TSMC process consistently show a 5-bit improvement in the effective number of bits (ENOB), e.g., from 7.5 before calibration to 12.4 after calibration. Experimental results for a 13-bit, 260 MS/s pipeline ADC demonstrate the feasibility of the proposed calibration scheme, showing a 20 dB improvement in the ADC’s signal-to-distortion ratio (accounting for $3^{rd}$ and $5^{th}$ harmonic distortion components) up to $f_{s}/4$ , and over a 13 dB improvement near the Nyquist frequency.