Hardware Implementation of Systolic Array Architecture using 4:2 Compressor Approximate Multiplier for Image Processing Operations

This research presents an innovative FPGA implementation of a $128 \times 128$ convolution systolic array architecture, optimized for image processing applications. The core of this design is a novel $8 \times 8$ dadda $4: 2$ compressor approximate multiplier, which offers a dynamic balance between computational precision and hardware efficiency. By configuring the systolic array with the multiplier, the design harnesses the inherent parallel processing capabilities of FPGAs to achieve high-throughput performance. The proposed dadda 4:2 compressor approximate multiplier introduces flexibility by enabling the adjustment of computational accuracy according to specific requirements, which is critical for various image processing tasks. This multiplier is integrated into a systolic array architecture, facilitating efficient operations. This architecture is utilized in edge detection of an image. The entire system is described using Verilog HDL and synthesized on the Xilinx Virtex-5 FPGA platform. A comprehensive evaluation is conducted to compare the performance of the dadda 4:2 compressor approximate multiplier against the exact multiplier. Key performance parameters such as area, delay, and power consumption are analyzed in detail. Results from this study indicate that the dadda 4:2 compressor approximate multiplier significantly reduces area (by $\mathbf{2 1. 2 4 \%}$), delay (by 56.95%) and hardware resource utilization without compromising essential computational accuracy. This advancement contributes to the development of adaptive and efficient hardware architectures.