Implementation of Turbo Product Code Decoder with High Throughput

This paper presents FPGA implementation of turbo product code decoder with single error correction BCH component codes. The implementation is based on Chase-Pyndiah algorithm which exhibits a modular and simple structure. Without compromising decoding performance, this decoder structure capable of supporting high throughput, fine parallelism, acceptable resource utilization. We simplified the algorithm of Chase decoding and modified extrinsic information calculation process to reduce computing complexity. We proposed a new decoding structure by computing several rows/columns at the same time and parallelized the SISO decoder. We pipelined the algebraic decoder and competing codeword finding module. The resulting turbo decoder is implemented on Xilinx xc7z045ffv900 platform with throughput up to 5.34M bps under 100MHz clock frequency. The resource consumed is also presented.