A High Gain Range Low Gain Step dB-Linear Programmable Gain Amplifier with Parallel Complementary Switching Current Method

This paper presents a Programmable Gain Amplifier (PGA) with a high gain range and a low gain step. By using the proposed Parallel Complementary Switching Current method, the voltage gain is controlled by changing the transconductance ratios between the Gain Stage and Load Stage. Besides, the paralleled Fine gain tuning circuits are used to reduce the gain step. Moreover, to increase the gain range, the Coarse gain tuning circuits are combined with the Fine gain tuning circuits in the parallel structure controlled by the simple Digital-cell circuits. The proposed PGA is implemented with TSMC 0.18- $\mu \mathrm{m}$ CMOS process. The worst simulated power consumption is 4.9 mW, and the minimum - 3 dB bandwidth is 14.7 MHz with a 12 pF capacitive load. The gain range is $\mathbf{4 6. 6 7} \mathrm{dB}$ (from - 23.54 to 23.13 dB) with a maximum gain error and maximum gain step of 0.265 dB and 0.746 dB, respectively, resulting in 64 selectable gain levels. The core area of the chip is $458.66 \times 558.53 \mu \mathrm{m}^{2}$.