The VLSI Architecture Design of a Configurable and High-Throughput Singular Value Decomposition Processor

This paper presents the algorithm and VLSI architecture of a high-throughput singular value decomposition (SVD) processor that decomposes matrices of any size, including nonsquare matrices. The SVD algorithm presented in this paper reduces the number of iterations and is more suitable for high-throughput engine design. The SVD architecture is designed based on the proposed algorithm and processing flow, where the hardware utilization of computing units is enhanced. Thus, the processing throughput is greatly enhanced while the complexity remains manageable. The proposed SVD processor is designed and implemented with the application-specific integrated circuits (ASIC) design flow of CMOS 90 nm technology. The performance estimations based on the post-layout simulations show that the throughput of 15384.6 k matrices per second is achieved at the cost of 210.64 kGE in terms of NAND gates. Compared with designs reported in the literature, the proposed SVD engine enhances the efficiency by 33%.