A Readily Driven Zoom ADC with Least-Significant Bit First Quantization for Brain-Computer Interface

This paper presents a zoom-based fast settling capacitive successive approximation register (SAR) analog-todigital converter (ADC) tailored for Brain-Computer Interface. The ADC mitigates the limitation of the front-end buffer’s driving capability by precisely adjusting the timing and reusing the coarse ADC digital code, effectively decreasing the equivalent load size of the front-end buffer. Moreover, when coupled with the truncated LSB first quantization technique (TLSBFQ), the number of bitcycles is reduced without introducing redundant bits. Compared to traditional LSBFQ technology, the proposed TLSBFQ structure requires fewer bit cycles to a certain extent. Consequently, the 12 -bit resolution zoom ADC achieves 11.5 ENOB (Effective Number of Bits) at a 1.8 V power supply and a typical 180 nm process. The power consumption of the zoom ADC is $5.36 \mu \mathrm{~W}$.