A flexible multi-standard I/O interface for chip-to-chip links in 65 nm CMOS

We present a flexible single-ended $40 \times 80 \mu \mathrm{~m}^{2}$ I/O cell optimized for source-synchronous links fabricated in a 65 nm CMOS process. The output driver operates from 1.2 V down to 400 mV signal swing and features configurable impedance, slew-rate control and termination. Each I/O cell contains one synchronous sense-amplifier-based flip-flop data receiver and an asynchronous clock receiver. The latter can be powered down in all cells receiving data. This flexibility allows errortolerant implementation of wide busses while minimizing power consumption. The configurability of the I/O interface allows driving off-package loads, while also satisfying requirements for chiplet interconnects. Measurements from wirebonded test chips show an energy efficiency of $0.5 \mathrm{pJ} / \mathrm{bit}$ for a 9 bit wide channel at $2 \mathrm{Gbit} / \mathrm{s}$ line rate and 400 mV signal swing for a PRBS-15 test sequence and $10^{-10}$ bit error rate.