Microelectronic EMC System Design for High Density Interconnect and High Frequency Environment

Due to increased clock speeds (today near 3 GHz/10 GHz in future) and data transfer rates (40 GBit/s) in the entire microelectronics area (partly also MEMS) arises an increasing demand for the efficient treatment of parasitic effects in the complete design process of microelectronic systems. In the future, no distinction between time and frequency response will exist (fT up to 110 GHz). I.e. digital, analogue design and RF design will grow together. In terms of high packing density, the different physical interferences (electronically-thermal- mechanical) have to be treated concurrently. These interferences have to be accounted for all along the design flow, starting from the early design stages, while refining the modelling and the simulation accuracy. The approach to improve EMC shall be related with other measures to improve signal-integrity (SI), robustness, functionality, power strategies, ESD, etc. to assure an integral system solution to optimally use intrinsic silicon capabilities. Therefore semiconductor manufacturers and their application customers have to deal with constraints on the chip level to meet electromagnetic compatibility (EMC) requirements of systems and subsystems and are therefore searching for suitable solutions. In the following a coherent approach to overcoming these problems at both chip and high-density packaging levels in the frame of the MEDEA+ project called MESDIE (A509 - Microelectronic EMC System Design For High Density Interconnect and High Frequency Environment) will be presented. In this contribution the thoughts regarding the MESDIE project concentrate on the aspects: • Application of IC in System Environments • Challenge of Packaging Technologies • Improved Design Methodology on HDP/HDI Level • Design to Noise Margin.