An Area-Energy Efficient EEG Detection System Based On PWL and Nonlinear SVM

This paper presents a low-power and area-efficient detection chip design for Support Vector Machine (SVM) classification of EEG signals. The design incorporates a 256-point FFT module for feature extraction of EEG signals. To further reduce power consumption and circuit complexity, an approximate computing approach is introduced for operations such as energy calculation, exponential functions and squaring. Additionally, a custom compression-based Lagrange multiplier encoding technique is employed. The proposed detection system has been implemented on FPGAs, achieving a $\mathbf{1 0 \% - 3 0 \%}$ reduction in resource utilization compared to recent related works, with power consumption as low as 0.201 W, significantly lower than existing solutions. In chip design, the energy efficiency reaches $0.31 \mu \mathrm{~J} /$ Class, which is an improvement of over 25%, and the area is reduced by more than 40%. Overall, the proposed detection system effectively reduces resource and power consumption through approximate computing circuits and encoding methods.