A High-Speed, Area-Optimized, ROM-Less (Co)Sine Wave Synthesis Accelerator

Sine and cosine wave synthesis is utilized for generating sinusoidal-alike values in the digital domain. While this task is handled through software, dedicated hardware like Direct Digital Synthesis (DDS) is also available. However, both methods rely on memory resources, such as look-up tables and Read-Only Memories (ROMs), which face latency limitations related to additional memory access times on top of additional Si area. With the advent of real-time arithmetic for sine wave approximation, this paper presents an all-in-one digital module that employs iterative multiply-accumulate (MAC) operations for sine and cosine synthesis, ready to be integrated in Systems-on-Chip (SoCs), Field Programmable Gate Arrays (FPGAs), or even standalone ASICs. Compared to ROM-less solutions like Taylor approximation, the proposed architecture achieves 80.80% lower resource utilization, 80.39% reduced propagation delay, and 36.66% higher accuracy in sine and cosine wave approximation, both operating as 32-bit systems with one sample per clock cycle.