Model Base Design of MIMO Transmitter and Receiver Implementation on an FPGA Board

This paper describes the implementation of the MIMO transmitter and receiver on an FPGA: Zynq UltraScale + MPSoC ZCU102 FPGA board. An HW/SW co-design environment designed and implemented the MIMO system on the FPGA board. The workflow including Matlab Simulink and Vivado converted a Simulink design to a Verilog HDL design. Codes for channel estimation and zero forcing operation block enabled the MIMO system. The transmitted IQ signals were loopbacked as IQ receiver signals inside the FPGA board. The designed MIMO system was implemented on the FPGA board to experimentally demonstrate the proposed MIMO system. The results verified that the MIMO system worked well on the FPGA board.