An Optimal PWM Method With Reduced Common-Mode Voltage and Current Ripple for Three-Phase Voltage-Source Inverter

Common-mode voltage (CMV) can cause various issues in applications, such as shaft voltage, leakage current, and electromagnetic interference (EMI). Active zero-state pulsewidth modulation (AZSPWM) is a classic and effective approach for mitigating CMV. However, this method compromises current quality, leading to undesirable CMV spikes and line-to-line voltage pulse reversals. In this article, an optimal AZSPWM (OP-AZSPWM) method is proposed to address these inherent issues in conventional AZSPWM. The proposed method utilizes the freedom of distributing the dwell times among four active vectors in conventional AZSPWM, and by optimizing the distribution, the current ripple is effectively reduced. In addition, an extra constraint is introduced to limit the minimum dwell time of the active vectors, thereby eliminating CMV spikes and pulse reversals. Comparative analysis against conventional AZSPWM demonstrates the superior performance of OP-AZSPWM in terms of current quality, CMV mitigation, and elimination of line-to-line voltage pulse reversals. Moreover, the proposed method can be easily implemented online using carrier-based modulation techniques. The effectiveness of the proposed method is validated through theoretical analysis, simulations, and experiments.