An Event-Triggered Asynchronous Incremental NS-SAR ADC Featuring Sampling-Rate Reconfigurability With Power-Scalability and Enabling AFE-ADC Co-Design Approach

The scarcity of asynchronous/self-clocked, sampling-rate ( $f_{s}$ )-reconfigurable, analog-front-end (AFE)-driven, incremental mode operation-based ADCs – highly needed for various practical event-triggered applications- pushes the need for innovative solutions. This paper is an effort in this direction and presents a $1^{\mathrm {st}}$ -order, versatile, asynchronous Incremental mode operation-based Noise-Shaping Successive-Approximation-Register (INS-SAR) Analog-to-Digital-Converter (ADC). Proposed for event-triggered multi-channel CMOS readout Application-Specific-Integrated-Circuits (ASICs), the proposed ADC is autonomously able to generate all required control signals internally by exploiting either a single externally-provided (for standalone ADC operation) or analog-front-end (AFE)-driven (for an integrated environment) trigger ‘Sample’ clock. The latter-mentioned characteristic enables an AFE-ADC co-design approach. Unlike all other proposed Incremental mode operation-based ADCs who offer sampling-rate ( $f_{s}$ )-reconfigurability with the tuning of an Over Sampling Ratio (OSR) value, this ADC features a novel $f_{s}$ -reconfigurability approach, even at a single OSR value, with an $f_{s}$ -scalable power-consumption. The ADC supports free-running/NS mode of operation too. The ADC has been designed and fabricated in a $0.35~\mu $ m CMOS process with two versions: $f_{s}$ -reconfigurable Version 1 operates at a supply voltage of 3.3 V, whereas the digital section of fixed $f_{s}$ Version 2 operates at 1.2 V. In incremental mode, both versions of the ADC achieve a measured ENOB of 10.25 bit, a peak SNDR of 63 dB, and a DR of 64 dB at an $f_{s}$ of 40 kHz with an OSR of 8. ADC Version 1 gets the same performance at all supported sampling-rates. ADC Version 1 power-consumption is $79~\mu $ W at its maximum $f_{s}$ of 167 kHz, while it is $40.56~\mu $ W for Version 2 at an $f_{s}$ of 132 kHz. The ${FoM}_{S}$ (155 dB) is constant for both versions and at all supported sampling-rates. With highly desired novel features and expected performance based on measurement results, the proposed ADC becomes a highly attractive candidate for multi-channel CMOS ASICs for a variety of practical event-triggered applications.