A Framework for Exploring Gate-Dielectric Materials for High-Performance Two-Dimensional Field-Effect-Transistors

The choice and engineering of the gate-dielectric (GD) is of paramount importance to the performance and energy-efficiency of two-dimensional (2D) field-effect-transistors (FETs) that are considered to be primary candidates for sub-10 nm gate length (L_g) metal-oxide-semiconductor FETs (MOSFETs). Despite remarkable progress achieved in recent years by the semiconductor-industry towards realization of high-performance 2D FETs based on transition-metal dichalcogenides (TMDs), achieving fast switching speeds and low device leakage currents remain an open challenge. More specifically, the effect of traps at the dielectric-2D interface and bulk defects in the dielectric on device performance have not been thoroughly investigated. In this paper, taking a common 2D-TMD material molybdenum disulfide (MoS₂) as an example, we explore various GDs and dielectric-stacks – their interfaces, traps and defects, by using rigorous ab-initio density-functional-theory (DFT) and non-equilibrium-Green's-function (NEGF) transport. Our framework and analysis provide valuable insights into the design of n-type 2D MoS₂ FETs, including their gate leakage (I_GL), subthreshold swing (SS), and ON-current (I_ON), and they can be extended to optimize the design and performance of other 2D FETs. More specifically, we demonstrate that monolayer (1L-) and bilayer (2L-) LaOCl/HfO₂ are promising GD stacks to achieve IRDS required values for I_GL, SS, and I_ON in n-type 2D FETs. Finally, we develop a framework to derive the design-window in terms of material/interface properties valid for both n-type and p-type 2D FETs and identify potential GD materials as a passivation/seeding layer across different L_g for n-type 2D FETs. The results highlight LaOCl as a promising candidate for L_g = 7 nm while several materials, including LaOCl and hBN, are viable for L_g = 10 nm.