A Wafer-level Package Design with Symmetrical Out-plane Electrodes for 3D-MEMS Devices

This paper describes a three-layer wafer-level package (WLP) scheme with lateral feedthrough signals and double-sided symmetrical out-plane electrodes for 3D MEMS devices. The WLP usually adopts the lateral signal routing scheme under the insulating layer or the vertical routing scheme based on TGV and TSV processes. SOI processes cannot easily place out-plane electrodes under the device layer. Therefore, a WLP scheme based on the SOG process and lateral signal routing is proposed and verified. The fabrication sequentially adopts anodic bonding and Au-Sn solid-liquid interdiffusion (SLID) bonding to realize the encapsulation of a stack of three layers and gap control of symmetrical out-plane electrodes by anchors and standoffs on device layer. Considering that the signal leads arranged under the insulation will face the risk of failure due to bonding pressure, this paper designs a novel signal lateral feedthrough scheme to improve the process yield. Shear strength test shows an average shear strength of 18.5MPa. Capacitance measurement is done to evaluate fabrication accuracy of out-plane electrodes. 8 dies from first fabrication flow have an average capacitance dispersion of 8.9%.