Accelerating Image Processing Functions on ZYNQ-FPGA Using the Vitis Vision Library

In the last decade, we have witnessed a high demand for high-resolution devices and screens. 4K and higher becomes a standard video definition, which requires special calculators such as DSPs, GPUs, TPUs, VPUs, and FPGAs. Among these accelerators, Xilinx has recently proposed a new system on chips -All programmable SOC, combining ARM processors and Artix-like mid-scale FPGA. Moreover, to facilitate implementation, Xilinx has upgraded their previous Vivado and Vivado HLS IDEs to the recent Vitis platform. In this work, we took advantage of these recent tools to design and implement higher-resolution image-processing applications on the PYNQ-Z1 board equipped with Zynq-7000 all-programmable SOC. We have accelerated OpenCV functions from the Vitis Vision Library by designing a processing system and programmable logic PS-PL scheme using Vitis HLS and Vivado. The co-design was ensured using the AXI interface to communicate between the PS and PL. Various image processing applications were designed and tested using Python in Jupiter Notebook. Results show that our co-design on the PYNQ-Z1 board accelerates edge detectors about 30× compared to the CPU implementation, while image filtering applications are accelerated by 10×. The project is available on GitHub.¹