High‐Level Synthesis (HLS)

Summary

Chapter 3 delves into High‐Level Synthesis (HLS) and its significance in modern digital design and electronic system design. HLS is the process of converting high‐level behavioral descriptions of digital circuits into register‐ transfer level (RTL) implementations, enabling designers to express designs in abstract, algorithmic manners using high‐level programming languages like C, C++, or SystemC. This chapter outlines the HLS process, including behavioral modeling, compilation, RTL generation, verification, and synthesis. It emphasizes HLS's advantages, such as increased productivity, faster time‐to‐market, improved design quality, portability, reusability, and efficient design space exploration. The chapter also discusses HLS's role in hardware acceleration, enabling software programmers to design hardware and bridging the gap between software and hardware design domains. Additionally, it explores common HLS languages and platforms, including CUDA, OpenCL, and Maxeler MaxJ, and their applications in hardware acceleration.