Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural Variations

We present a novel multi-task learning (MTL) approach with shared representation for the real-time extraction of Berkeley Short-channel IGFET Model-Common Gate (BSIM-CMG) parameters in nanosheet field-effect transistors (NSFETs) with multiple structural variations. An innovative artificial neural network (ANN) architecture, coupled with specialized training strategies, was introduced to extract BSIM-CMG parameters in NSFETs with varying gate lengths ( $L_{\mathrm {g}}$ ), nanosheet widths ( $W_{\mathrm {ns}}$ ), and thicknesses ( $T_{\mathrm {ns}}$ ). To mitigate overfitting due to disparate data sources, such as Monte Carlo simulations for training data and technology computer-aided design (TCAD) simulations or hardware measurements for test data, additive noise was incorporated into the training data. Optimal test accuracy was achieved with maximum noise levels of 10% for $I_{\mathrm {d}}$ and 2% for $C_{\mathrm {gg}}$ . The MTL approach, leveraging shared representation, effectively captured relationships among input-output groups, reducing the risk of biased ANN training toward any specific group. The proposed method was evaluated using a 1.4 nm node NSFET and eight additional NSFETs with $L_{\mathrm {g}}$ , $T_{\mathrm {ns}}$ , and $W_{\mathrm {ns}}$ variations of 1, 0.5, and 5 nm, respectively, from the baseline values of 12, 5, and 25 nm at the 1.4 nm node. The MTL-based ANN successfully extracted BSIM-CMG parameters for both $I_{\mathrm {d}}$ and $C_{\mathrm {gg}}$ , yielding low relative modeling errors of 4.26% for $I_{\mathrm {d}}$ and 0.709% for $C_{\mathrm {gg}}$ . Additionally, the method was validated using 3 nm node hardware NSFETs and nanowire FETs with varying $L_{\mathrm {g}}$ and nanowire diameters, demonstrating its versatility across different technology nodes and device architectures.