Reliable Network-on-Chip Design with Spare Node Analysis for Smart Fault Management

Networks-on-Chip (NoCs) are crucial in VLSI development, enabling faster on-chip communication. However, as technology advances, power consumption by NoC links competes with that of routers and network interfaces. To address this, an encoding technique using XOR gates is proposed to reduce link power consumption. This innovative design introduces robust error detection mechanisms for dynamic Network-on-Chip (NoC) architectures, where faulty blocks' count and location fluctuate during operation. Real-time detection of data packet errors and adaptive routing algorithm anomalies enables precise identification of permanent and transient faults, pinpointing faulty blocks with high accuracy.Intelligent spare node selection in NoC routers leverages this information, maintaining optimal throughput, network load, and data packet latency. By minimizing redundant checks on inactive nodes, return path latency is significantly reduced. This approach optimizes NoC performance, rendering it a promising solution for dependable and efficient on-chip communication.