Design of Current Mode CMOS Multiplication Circuits Based on Trans-Linear Loops

In this paper, a low-power, high-precision current mode CMOS multiplication circuit design method is proposed. Using the square characteristic of NMOS operating in the saturation region to form a trans-linear loop, the multiplication square term equation can be derived, and on this basis, the multiplication circuit and division circuit are designed. The multiplication circuit is also combined with the power expression of the logic function to complete the design of the basic current mode CMOS logic gate circuit, which constitutes the complete set. Simulation is performed using Pspice under 180nm CMOS process parameters, and verification of the circuit shows that the power consumption of the multiplication circuit is $0. 333\mathrm{W}$, linearity error is 0.8%, full harmonic distortion THD 1.59%, the circuit structure is simple, the results show that the circuit has low power consumption and high accuracy.