Data Rearrangement Optimized FIR High-Pass Filter Implemented on FPGA

Filtering plays a crucial role in digital signal processing systems. Filters are required to meet the demands of high precision in signal separation and high-speed processing. It is still challenging to improve the filtering speed while maintaining high accuracy. In this study, a high performance finite impulse response (FIR) high-pass filter based on FPGA which supports floating-point computation is presented. The strategy of computation data rearrangement is used to efficiently store and retrieve raw data and intermediate value. On the other hand, a high-speed data transmission system was established for the filter module to reduce clock delays caused by data waiting, thereby the filtering speed is further enhanced. After implementation on FPGA, the results indicate that the filter achieves high filtering accuracy while significantly enhancing filtering speed. This design achieved high accuracy with only 0.39% to 1.95% mean square error, and a filtering speed of 0.0017s, representing a 470-fold increase in filtering speed compared to the model implemented on a CPU platform and 1.50-fold higher than our previous report.