Design of 6T XOR Gate Using Cadence in 45nm 90nm &180nm Technology

The XOR gate is a fundamental component in digital electronics which are crucial for constructing binary adders, enabling arithmetic operations in computers. Proposed study presents the design and comparative analysis of a 6 T XOR gate implemented in $45 \mathrm{~nm}, 90 \mathrm{~nm}$, and 180 nm CMOS technologies using Cadence tools. The aim is to assess the performance metrics such as power consumption and delay for each technology node. The methodology involves creating the schematic design, followed by symbol representation, and culminating in the creation of a test circuit. The truth table is then verified through waveform analysis. Subsequently, delay and average power are calculated across various technologies. A comparative analysis is conducted to ascertain which technology exhibits minimal delay and optimal power consumption. As we scale down the technology from 180 nm to 45 nm in CMOS XOR gate design, both power consumption and delay decrease, leading us to conclude that 45 nm technology is optimal.

I. Introduction

This work focuses on developing a new XOR-cell to achieve full swing voltage for high-speed operation, serving as a fundamental unit for various full adders [1]. The efficiency of full adders, crucial for speed, power consumption, and driving capacity, heavily depends on circuit performance [2]. In the realm of portable electronics, rapid, compact, and low-power digital circuits are essential. Fast addition operations are critical for high-speed processors [3]. As technology advances, there is a growing demand for swift and precise processing devices. Adders are fundamental for arithmetic operations, relying on efficient XOR-gate design [4]. To address the needs of battery-powered applications, research explores low-power strategies in CMOS circuits, incorporating minimal supply voltage and optimizations in architecture, logic design, circuits, and technology [5].