An Efficient PFSCL based D-Latch Design Using Dynamic-Threshold Voltage MOSFET

This paper introduces an effective D-Latch design for PFSCL utilizing Dynamic Threshold Voltage MOSFET (DTMOS). In this proposed design, DTMOS transistors replace pull-down transistors, resulting in reduced threshold voltage and overall voltage supply demand, thereby enabling operation with an ultra-low voltage supply of 0.8 V. A comparison between the proposed PFSCL D-Latch design and an available triple tail cell-based design was conducted to evaluate effectiveness. Several SPICE simulations were performed using 45nm PTM CMOS technology parameters to confirm the functionality of both designs.