Realization of Zero Measurement Dead Time on FPGA-Based Time-to-Digital Converters

Although the time-to-digital converters (TDCs) implemented on field programmable gate arrays (FPGAs) have achieved considerably high measurement resolution and precision in recent years, achieving zero measurement dead time is still a challenge for some applications. The goal of this article is to design an FPGA-based TDC with zero measurement dead time without compromising other performance. Based on the conventional tapped delay line (TDL) TDC structure, the idea of our method is to enable the continuous flow of trigger signals onto the TDL and propose a powerful encoder with the capability of recognizing all trigger edges within a system clock period. Considering the inherent “bubble” problem in the TDL, the latched TDL status is first decomposed into 16 divisions, all of which identify all the trigger edges in parallel. Through a specific coincident mechanism, the trigger edges on all the divisions are matched and their positions on the TDL are encoded for output. To overcome the significant integral nonlinearity (INL) error caused by large delay deviations of delay units, online calibration tables are established to convert the positions of trigger edges into fine timestamps so that the original resolution and precision of the TDC can be maintained. The proposed TDC is implemented on a Xilinx Zynq UltraScale+ FPGA for performance evaluation. In addition to verifying the TDC function and online calibration tables, the TDC resolutions for the rising and falling edges are measured as 1.82 and 1.92 ps, respectively. By inputting the trigger signals with a higher frequency than the TDC system clock, all the rising and falling edges of trigger signals are detected with the root-mean-square (rms) measurement precisions ranging from 2 to 4.5 ps, which confirms the achievement of zero measurements dead time.