Asymmetric Regular Sampling VSFPWM for Circulating Current Control in Paralleled Interleaved Multilevel Inverters

Parallel interleaved multilevel inverters (PIMIs) hold substantial potential for high-power applications, but their inherent circulating current issue leads to increased current stress and reduced system efficiency. This article focuses on phase circulating current (PCC) suppression in PIMIs. First, a PCC prediction model is proposed, considering a one-control-cycle delay when applying the asymmetric regular sampling (ARS) rule. By employing this model, appropriate redundant vectors are selected to achieve an approximately 50% reduction in PCC. Then, another PCC prediction model is developed, incorporating a two-control-cycles delay. Utilizing this model, an ARS-based variable switching frequency pulsewidth modulation (VSFPWM) is proposed to precisely control the peak value of PCC, and a method for determining the boundary of the switching frequency is suggested. The proposed VSFPWM explores the capability of the pulsewidth modulation (PWM) algorithm to effectively control PCC under low-switching frequency and low-carrier ratio conditions by using two degrees of freedom: vector selection and switching frequency. Finally, the effectiveness of the proposed strategy is validated by experiment with a 36-MVA inverter.