A Ripple Reduction Technique for Single Stage Switched Capacitor Converter in Ultra Low-Power Applications

One of the primary concerns in the design and practical use of fully integrated switched capacitor (SC) DC-DC converters is their load-dependent output voltage ripple. In this paper, an all-digital control technique to reduce the output ripple of fully integrated SC converters for ultralow-power and, low-noise applications is presented. The core SC converter is regulated using lower-bound hysteretic control, whereas the proposed ripple reduction control loop uses a two-step coarse-fine tuning approach to reduce the output voltage ripple. Coarse ripple reduction control is implemented by modulating the flying-capacitance, whereas fine ripple reduction control is implemented by modulating the switch on-resistance. The proposed method is adaptive to load changes and can operate from no-load up to $250\mu $ A full load. The developed mathematical model of the ripple and its reduction loop can be extended to any step-down ratio SC converter topology. A 2:1 step down ratio SC converter with the proposed adaptive ripple reduction control loop (RRL) is designed and fabricated in 180nm CMOS technology with 6 layers of metal, using only core transistors. Characterization results show that, when the RRL is enabled, the output voltage ripple reduces from 45.6mV down to 16.5mV for an output voltage of 800mV and a load current of $100\mu $ A, closely matching the mathematical model of the cancellation loop. The converter occupies a die area of 0.606mm2 including the flying-capacitor and output capacitor and achieves a peak efficiency of 70.49%.