VbPWM-Based ADT: An Iterative Deduction Approach Restricting the Traversal of MPWM at the Cost of In-Band SNR

Based on the concept of mapping-based pulse width modulation (MPWM), the look-up-table-based all-digital transmitter (LUT-based ADT) achieves high signal-to-noise ratio (SNR) and low error vector magnitude (EVM) by leveraging a stored mapping from the baseband complex sample to the output binary sequence, while its high RAM consumption and LUT generation complexity hinder its further usage. Toward a RAM-free and traversal-free ADT based on MPWM, in this paper, we model the MPWM process as an optimization problem and correspondingly construct a Viterbi-based PWM (VbPWM) modulator scheme, featuring real-time deduction of the 1-bit sequence from the input complex sample and a traversal-free computation process. Fixed points simulations suggest that the deduced local optimum demonstrates a 10 dB SNR loss compared with the global optimum of MPWM, while this loss can be further eased by 2-3 dB after introducing a simplified simulated annealing algorithm. Additionally, a fully serial and pipelined implementation structure is proposed to unfold the iterations into cascading iteration units, thereby achieving run-time reconfigurable carrier frequencies and minimizing block read-only memory (BRAM) usage. EVMs of the proposed ADT with carrier frequencies ranging from 0.6 GHz and 7.6 GHz under different symbol rates are measured with ZCU102, presenting an increasing trend associated with carrier frequency and symbol rates. Consequently, compared with the original MPWM, a 1% loss of EVM is revealed under 5 MBaud of symbol rate for all measured frequencies. The maximum EVM under 5 MBaud is measured as 3.5%, while the maximum for 25 MBaud and 50 MBaud is 5% and 5.8%, respectively. The RAM usage is then minimized to a single 36K tile and the traversal of MPWM is removed.