Evaluation of Fin Geometry and Threshold Voltage Variants on Single-Event Effects in 7-, 5-, and 3-nm Bulk FinFET Technologies

Technology computer-aided design (TCAD) simulations are used to clarify the underlying mechanisms affecting single-event upset (SEU) results at 7-, 5-, and 3-nm bulk FinFET technologies using hard-biased, inverter, and latch configurations. The parameters varied for irradiation tests and simulations are threshold voltage ( $V_{\text {T}}$ ) and fin geometry. Results show that estimated changes in geometry and process parameters across these technology generations have minimal effects on the collected charge, whereas circuit-level parameters strongly influence the collected charge, single-event transient (SET) pulse widths, and, subsequently, SEU cross sections.