Design of Error-Resilient Approximate Multiplier for Image Processing Applications

In the ever-growing quest for efficient computing, approximate multipliers offer a compelling trade-off between accuracy and resource consumption. This work delves into the design of such multipliers, targeting three crucial aspects: efficiency, error resilience, and its application. The idea to propose an approach that leverages truncated partial products and strategically placed approximations to significantly reduce hardware complexity compared to exact multipliers. This enables substantial savings in area, making the design ideal for applications with tight resource constraints. However, reducing complexity often comes at the cost of increased errors. To combat this, integration of error recovery modules adapted from existing research is proposed. Significantly reduces error metrics like ED, NMED and MRED, ensuring acceptable accuracy for targeted applications. Furthermore, inherent biases can creep into approximate multipliers, skewing their outputs. This will further refine the accuracy of the design, solidifying its potential in a wider range of real-world scenarios. Overall, this work paves the way for highly efficient and adaptable approximate multipliers. By balancing resource savings with error control and bias mitigation, a promising alternative for applications where computational power and flexibility is offered. The obtained results are further applied into image processing applications and is proved to be fruitful. Paper proposes a novel 4:2 approximate compressor which comparatively takes 20% less area with an approximate increase an error in 10% which is proven to be acceptable. This paper also goes with the six bit truncation which improves the compute time, area and PDP.