An SRAM-based Error-Free Time Domain Pulse Train Computing-In-Memory Macro achieving 226.14 TOPS/W and 5.782 TOPS/mm2

This paper presents an SRAM-based input bit configurable pulse-train computing-in-memory (CIM) macro for edge devices. The proposed macro computes matrix-vector-multiplications (MVM) in a bit-wise manner, generating pulse trains to overcome the limited signal margin and variations occurring in analog time-domain SRAM-based CIM macros. Furthermore, the system architecture comprises an error-free dynamic OR gate discharge computation, effectively addressing the non-linearity associated with analog computation methods. It also incorporates a dual pulse counter, which enhances the throughput of the system while maintaining high energy efficiency. The prototype 4Kb pulse train SRAM CIM was implemented using 28-nm CMOS technology, achieving 226.14 TOPS/W energy efficiency and a 5.14× increase in area efficiency compared to the state-of-the-art reaching 5.782 TOPS/mm2.