APAPG: Address Pre-Processed ALPG for High-Speed Linear Test

To test the high-speed and high-capacity memories, an algorithmic pattern generator (ALPG) is integrated within the automatic test equipment. However, due to the execution of complex operations, ALPG operates slower than the latest memories, making it challenging to conduct at-speed tests. To address this speed discrepancy, an address pre-processed ALPG (APAPG) is proposed in this paper. APAPG enables high-speed pattern generation by exploiting the differing behaviors of the upper and lower bits of the address during linear pattern generation. The monotonously changing upper bits are generated based on counters, while the complex yet repetitive lower bits are pre-processed and then fetched. Since only simple arithmetic and branching operations are performed during testing, APAPG can operate faster than previous ALPGs. In addition, N-way interleaving can also be applied. Although increasing N for further speed-up, the hardware overhead of APAPG does not increase proportionally, indicating good hardware efficiency.