Constructing Hardware Accelerators for Number-Theoretic Transform Using High-Level Synthesis

The rapid advancements in quantum computing threaten traditional public-key cryptosystems, necessitating the development of quantum-safe cryptographic solutions like post-quantum cryptography and lattice-based cryptography. However, the widespread adoption of these technologies is hindered by the computational intensity of operations such as polynomial multiplication over rings. Although the Number Theoretic Transform (NTT) is used to speed up the polynomial multiplication, but it remains the main bottleneck in terms of latency. This paper presents an NTT accelerator that utilizes memory bank division and high-level synthesis with pipelining techniques in a 28nm CMOS process. The proposed accelerator supports a wide range of polynomial degree, reduces latency by a factor of up to 7.2, and minimizes area by a factor of 2.8-5.1 compared to prior art.