Performance Projection of Gate-All-Around (GAA)-Based Negative Capacitance Complementary FET (NC-CFET) Relative to Standard CFET

In this article, we have compared the negative capacitance complementary FET (NC-CFET) from a device-circuit perspective with the experimentally demonstrated CFET. NC-CFET could potentially offer additional advantages over conventional CFET, like enhancement in the sub-threshold behavior, reduction in threshold voltage variability, improvement in noise margin, low supply voltage, and high-speed operation, etc. The comparative study shows the improvement in the logic devices, as well as SRAM memory cell with the use of negative capacitance concept. Detailed circuit-level simulations have been used to analyze the performance gains with NC-CFET. Further, we have demonstrated multi layer NC-CFET with vertically stacked N/P channels for ON-current matching, symmetric inverter switching, and improved static noise margin (SNM) in SRAM.