Development of SC Polar Decoder Design Scenario for 5G/6G Telecommunications Applications

The paper considers hardware concepts for implementing a polar decoder based on a Field-Programmable Gate Array (FPGA). The data flow diagram of the successive cancellation (SC) decoder and the scheduling of the partial sum (S) calculation sequence are analyzed. The advantages of the semi-parallel successive cancellation (SPSC) decoder are shown, the decoder delay is determined for different frame lengths. This is achieved by the given architecture of the SPSC decoder, as well as the described architecture of the block for calculating S. A study of a model of a telecommunication channel with polar coding (PC) for different code rates and different digital modulation multiplicities is carried out. The capabilities of the adaptive modulation format and PC for implementing the required channel bandwidth are investigated. It is expected that the results will be useful in developing PC decoders for 5G/6G systems.