Signal Integrity of Die-to-Die Interface with Advanced Packages for Co-Packaged Optics

To meet the high demands in Artificial Intelligence (AI) and Machine Learning (ML) applications, the conventional electrical interconnect has limitations on bandwidth, latency, and power consumptions. Co-Packaged Optics (CPO), and advanced heterogenous integration of optics and silicon on a single package, has attracted much attention to achieve higher bandwidth and power efficiency. Samsung has dedicated to develop advanced packaging technologies, such as 2.5D I-CubeS with a silicon interposer, 2.3D I-CubeE with an embedded silicon-bridge and organic redistribution layer (RDL), 2.3D I-CubeR with an organic RDL, and 3D X-Cube with a fine bump pitch Thermocompression Bonding (TCB) and hybrid Cu bonding. Using ICubeS or I-CubeE technologies, the feasible CPO architecture can be built by optoelectronic engine arrangement, stacking of photonic integrated circuit (PIC) and electronic integrated circuit (EIC), and PIC coupling type. This paper presents the signal integrity of die-to-die (D2D) interface for the logic of XPU to the logic of EIC. The signal integrity under simplified I/O models for a transmitter and receiver, W-element interconnect of Si-bridge, and through-silicon via (TSV) in the PIC was compared and verified from Universal Chiplet Interconnect express (UCIe) specification.