Retention Characteristics Dependent on High-κ Gate-Insulator Stack in Hf-ZnO Synaptic Thin-Film Transistors

In this paper, we present a study on a retention characteristics dependent on a high- $\kappa $ gate insulator stack in synaptic thin-film transistors (Syn-TFTs) with a Hf-ZnO channel layer. A memory function of Syn-TFTs can be implemented in a gate insulator, where electrons are trapped with applying positive programming pulses to a gate terminal. This is usually realized in a flash memory structure with the tunneling oxide (T-Ox). As a simple structure, the gate insulator without the T-Ox can also be used, where traps associated with defects are intentionally playing the role as charge trapping sites. Here, depending on the presence or absence of the T-Ox in the gate insulator, it is anticipated that both the weigh-update characteristics (e.g., a programming speed) and retention characteristics (e.g., a retention time) of the Syn-TFTs are varied. To verify this, the pulsed characteristics of the fabricated Syn-TFTs with different gate-insulator structure (i.e., the fabricated Syn-TFTs with and without the T-Ox) are monitored experimentally. From experimental results, it is found that the programming speed of the Syn-TFT without the T-Ox is faster compared to the Syn-TFT with the T-Ox, meaning a higher sensitivity. On the other hand, the extracted retention time of the Syn-TFT with the T-Ox is longer than that without the T-Ox. These suggest a trade-off relation between the sensitivity and retention time depending on whether the T-Ox exists in the gate insulator stack.