A Low Power Oriented Multiple Target Test Generation Method for 2-Cycle Gate-Exhaustive Faults

In recent years, the progress of VLSIs has caused an increase in the number of cell-internal defects in addition to signal line defects. In this paper, we focus on a fault where the transition on the output signal line of a cell is delayed in each input pattern combination of the gate due to cell-internal defects when the transition occurs on the output signal line of the cell. This fault model is called as a 2-cycle gate-exhaustive fault. In VLSI testing, high power consumption might occur because many faults are tested by a test vector from the view point of test cost reduction. However, high power consumption causes erroneous tests due to excessive IR drop, resulting in yield loss. Thus, this paper proposes a low power oriented multiple target test generation method for 2-cycle gate-exhaustive faults using pseudo Boolean optimization.