A Low Power Fully-Static Contention Free-Flip-Flop With Reduced Clock Load

The brief presents a low-power redundant transition-and contention-free flip-flop with fewer clock transistors. Called reduced clock-load flip-flop (RCLFF), the proposed flip-flop minimizes the clock load by merging clock transistors to reduce the clock power consumption regardless of input switching activity. It also provides completely redundant transition-free operation, further reducing the power consumption. Reliable operation with no floating node and contention can enable further power saving by letting the flip-flop in the near-threshold voltage (NTV) region. Performance evaluation in a 28-nm CMOS process indicates that RCLFF achieves up to 60.9% power reduction compared to conventional flip-flops at 0.1 switching activity. By reducing power consumption with moderate DQ latency, the power-delay product (PDP) of RCLFF is improved by up to 64.5%. The Monte-Carlo simulation result reveals that RCLFF can operate reliably down to a 0.3 V supply voltage regardless of process, voltage, and temperature (PVT) variations.