RV-ProViler: Evaluating RISC-V ISA for Application-Specific Requirements

RISC-V instruction set architecture (ISA) is gaining momentum as an open-source ISA that allows the implementation of a wide range of processor designs. These processor designs can tackle diverse application scenarios, from embedded processing to high-performance computing. RISC-V ISA has a modular architecture, with different base ISAs and optional standard extensions to choose from. RISC-V ISA in itself is quite diverse and requires a platform to profile the application to estimate which extensions and ISA configurations fit best for a particular application. RISC-V also provides an open-source toolchain and a Spike simulator that can be used to simulate an application. In this work, an open-source profiling tool is presented for evaluating RISC-V ISA specification for an application called RV-ProViler. The profiling tool uses bash a nd Python scripts to couple the RISC-V toolchain and the Spike simulator to generate a histogram that details the instruction coverage of an application or a function for a particular RISC-V extension. To demonstrate the usability of the tool, different functions are used as a test case; matrix multiplication, convolution, max-pooling, and fully connected functions, to benchmark the P- (packedSIMD) and the V-extension (vector instructions) of RISC-V. A Lenet-5 algorithm is also used as a test case to show a comparison between base ISA (RV32IM), P-extension (RV32IMP), and V-extension (RV32IMV). The results show a maximum speed-up of $5.87 \times$ when using P-extension and $16.52 \times$ when using V extension for matrix multiplication. For Lenet- 5 a speed-up of $4.09 \times$ when using P-extension and $9.58 \times$ when using V-extension was observed.