Cycle Count Estimation of VLIW Processors Using Machine Learning

Fast evaluation is important for processor design space exploration in order to increase the probability of encountering the optimal design in the vast space of configurations. Previous work has focused on estimation of dynamic multi-issue processors, which does not consider the effects of a varying instruction-set on the estimation through heuristic compilation. This paper presents a cycle count estimation method for application-specific static multi-issue processors with customizable datapaths via machine learning techniques that can estimate cycle counts for any architecture configuration after the initial profiling of the program. Among the estimated models, the residual neural network model achieves the lowest mean relative error of $4.7 \%$ while being orders of magnitude faster than running the recompilation and simulation steps.