Low Power Estimation for Multibit Memory Writing and Reading in Hardware Chip Design

The development of parallel programming models can be traced back to the parallelism and hardware synchronization verification that is required for an architecture to perform its intended functions. The research article focuses on power estimation for multibit memory operation of writing and reading in hardware chips. The design is considered for 16 memory registers having 8-bit data synchronized with a single clock. The performance of the chip is analyzed for different sizes of input data with the hardware chip parameters such as power consumption, frequency, and delay. The parallel data processing in the registers helps for optimal delay and power estimation in the hardware. The chip simulation is verified on the Virtex-5 FPGA hardware kit for different data sizes.