Novel Hybrid Low-Resource Field-Programmable-Gate-Array Time-to-Digital-Converter Architecture

Time measurements are challenging in electronics given their various applications. The main focus lies not in achieving greater precision, as conventional architectures have already reached picosecond levels. Instead, the challenge stems from the use of low resources and the substantial expansion in the number of channels. This study presents a novel architecture for the implementation of time-to-digital converters (TDCs) in applications where resources are constrained. The introduced field-programmable-gate-array (FPGA)-based TDC offers a resolution of 415.84 ps, a single-shot precision of 0.45 least significant bits (LSBs) (186 ps r.m.s.) while maintaining a minimal resource occupancy. Built upon a multishift phase counter, the TDC is extended with a tap delay using the input delay available in the FPGA hardware input, doubling the resolution of the TDC. The resource utilization is minimized when compared to low-resource state-of-the-art TDCs. The number of look-up tables (LUTs) has been reduced to 102, and the number of registers to 213. Furthermore, the presented TDC exhibits favorable differential nonlinearity (DNL) (0.2 LSBs) and integral nonlinearity (0.15 LSBs). The TDC has been successfully implemented on an Artix7-2 from Xilinx. This design provides a resource-effective solution for applications requiring high precision and low resource consumption.