A Single-Stage 24 Gb/s 8:1 Cryogenic Multiplexer for Josephson Arbitrary Waveform Synthesizer

This work presents a single-stage 8:1 current mode logic (CML) multiplexer (MUX) with integrated active baluns at the inputs within the block and clock distribution network with $\mathbf{1 2. 5 \%}$ duty cycle clock generation. It is intended for constructing a highly integrated cryogenic high-speed system-on-chip (SoC) with a return-to-zero converter and a current buffer intended to drive Josephson Arbitrary Waveform Synthesizers (JAWS). Usually, 8:1 MUX consists of seven 2:1 MUX gates and three clock signals at different frequencies. This results in increased power consumption and a complex clock distribution. The proposed single-stage 8:1 MUX solution simplifies system realization. The chip is realized in a $0.13 \mu \mathrm{~m}$ BiCMOS process. The chip was measured at data rates from $800 \mathrm{Mb} / \mathrm{s}$ up to 24 $\mathrm{Gb} / \mathrm{s}$ with a ±123mV single-ended voltage swing on a $50 \Omega$ load at room temperature (RT). The core chip area is $0.132 \mathrm{~mm}^{2}$ and DC consumption is 224 mW. To author’s knowledge this is the first single-stage 8:1 MUX for driving JAWS measured at 16 K.