Area-Aware Logic Mapping for MAGIC based In-Memory Computing

In-memory computing offers promising prospects for data-intensive applications, with memristor-aided logic (MAGIC) presenting a notable avenue. Logic synthesis for MAGIC-based systems entails mapping Boolean functions to memristor crossbars, where previous efforts often suffer from accurately evaluating multi-fanout node costs. In this paper, we propose a heuristic logic mapping method tailored for MAGIC-based in-memory computing, specifically addressing multi-fanout nodes’ challenges. In addition, we also propose an automated equivalence checking methodology aimed at validating the correspondence between the design specification and the resulting micro-operations post-mapping. Our proposed method yields substantial improvements, with an average reduction of 13% and 10% in the requisite non-volatile memory when compared to state-of-the-art techniques across the ISCAS’85 and IWLS’93 benchmarks. Remarkably, these enhancements are achieved with only marginal increases of 1% and 2% in the required computation cycles.