A Proposed PWM Technique to Reduce Circulating Current in Two Parallel Interleaved Two-Level VSIs

By connecting inverters in parallel, a grid-connected converter system’s power processing capability can be improved. It has benefits including efficiency, dependability, and adaptability. However, there exists an instantaneous voltage mismatch between the inverter. This voltage mismatch may arise due to following situations: (i) phase shifting the carriers of the two inverters for interleaved pulse width modulation; (ii) running both VSIs at different power levels; and (iii) hardware problems such as dead time discrepancies, component limitations, etc. This instantaneous voltage difference produces a circulating current between the inverters. As a result, the efficiency of the overall system reduces. This paper proposes a carrier-based pulse width modulation approach to decrease circulating current in parallel connected 3- $\phi$ VSIs (equal distribution of power) running with interleaved PWM. To validate the PWM technique suggested, simulation data as well as a mathematical model are provided.